Commit 15ebfd1e authored by Paul Boven's avatar Paul Boven
Browse files

Re-idented main.vhd

parent 756544f9
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
-- Company: CAMRAS (www.camras.nl)
-- Engineer: Paul Boven
--
-- Create Date: 22:32:44 11/28/2016
-- Design Name:
-- Module Name: main - Behavioral
-- Project Name:
-- Project Name: DT Backend - SDR mode (5MHz BW)
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Description: Reduces the 70MS/s data stream to a 5MHz bandwidth centered
-- around 21.4 MHz. Send data as I/Q pairs, 16 bit interleaved
-- to be compatible with GnuRadio.
-- Dependencies:
--
-- Revision:
......@@ -163,104 +164,104 @@ port map(clk => clk,
-- Rotate spinner at 2 Hz --
process(clk)
begin
begin
if rising_edge(clk) then
if spinner_count < 70000000 then
spinner_count <= spinner_count + 1;
else
spinner_count <= (others => '0');
clk_1hz <= not clk_1hz;
end if;
if spinner_count < 70000000 then
spinner_count <= spinner_count + 1;
else
spinner_count <= (others => '0');
clk_1hz <= not clk_1hz;
end if;
end if;
end process;
end process;
-- This design assumes that the 'rfd' signal on both FIRs is constantly toggling at 70 MHz
-- so 'rfd' is not checked. It also assumes that fir_I and fir_Q will always be exactly syncrhonous
process(clk)
begin
begin
if rising_edge(clk) then
adc_clk_sig <= not adc_clk_sig;
sample_ram(to_integer(pkt_idx_buf)) <= ram_buf;
pkt_idx_buf <= pkt_idx;
din_I <= std_logic_vector(buf_I_buf(25 downto 10));
din_Q <= std_logic_vector(buf_Q_buf(25 downto 10));
buf_I_buf <= buf_I;
buf_Q_buf <= buf_Q;
buf_I <= sample_buf2 * lo_I_buf;
buf_Q <= sample_buf2 * lo_Q_buf;
lo_I_buf <= lo_I;
lo_Q_buf <= lo_Q;
sample_buf2 <= sample_buf;
if(adc_clk_sig = '1') then
sample_buf <= resize(signed('0' & adc_a) -512, 10);
if lo < 349 then
lo <= lo + 1;
else
lo <= (others => '0');
end if;
end if;
if(rdy_I = '1') then -- buffer the 16 bit FIR outputs
fir_I_buf <= dout_I;
fir_Q_buf <= dout_Q;
interleave <= lsb_I;
elsif interleave = lsb_I then
ram_buf <= fir_I_buf(7 downto 0);
interleave <= msb_I;
pkt_idx <= pkt_idx + 1;
elsif interleave = msb_I then
ram_buf <= fir_I_buf(15 downto 8);
interleave <= lsb_Q;
pkt_idx <= pkt_idx + 1;
elsif interleave = lsb_Q then
ram_buf <= fir_Q_buf(7 downto 0);
interleave <= msb_Q;
pkt_idx <= pkt_idx + 1;
elsif interleave = msb_Q then
ram_buf <= fir_Q_buf(15 downto 8);
pkt_idx <= pkt_idx + 1;
interleave <= idle;
if(pkt_idx < 2**PKTSIZE -100) then -- start transmitting when packet is nearly full
tx_start <= '0';
else
tx_start <= '1';
end if; --pkt_idx
end if; -- interleave
adc_clk_sig <= not adc_clk_sig;
sample_ram(to_integer(pkt_idx_buf)) <= ram_buf;
pkt_idx_buf <= pkt_idx;
din_I <= std_logic_vector(buf_I_buf(25 downto 10));
din_Q <= std_logic_vector(buf_Q_buf(25 downto 10));
buf_I_buf <= buf_I;
buf_Q_buf <= buf_Q;
buf_I <= sample_buf2 * lo_I_buf;
buf_Q <= sample_buf2 * lo_Q_buf;
lo_I_buf <= lo_I;
lo_Q_buf <= lo_Q;
sample_buf2 <= sample_buf;
if(adc_clk_sig = '1') then
sample_buf <= resize(signed('0' & adc_a) -512, 10);
if lo < 349 then
lo <= lo + 1;
else
lo <= (others => '0');
end if;
end if;
if(rdy_I = '1') then -- buffer the 16 bit FIR outputs
fir_I_buf <= dout_I;
fir_Q_buf <= dout_Q;
interleave <= lsb_I;
elsif interleave = lsb_I then
ram_buf <= fir_I_buf(7 downto 0);
interleave <= msb_I;
pkt_idx <= pkt_idx + 1;
elsif interleave = msb_I then
ram_buf <= fir_I_buf(15 downto 8);
interleave <= lsb_Q;
pkt_idx <= pkt_idx + 1;
elsif interleave = lsb_Q then
ram_buf <= fir_Q_buf(7 downto 0);
interleave <= msb_Q;
pkt_idx <= pkt_idx + 1;
elsif interleave = msb_Q then
ram_buf <= fir_Q_buf(15 downto 8);
pkt_idx <= pkt_idx + 1;
interleave <= idle;
if(pkt_idx < 2**PKTSIZE -100) then -- start transmitting when packet is nearly full
tx_start <= '0';
else
tx_start <= '1';
end if; --pkt_idx
end if; -- interleave
end if; --rising_edge(clk)
end process;
end process;
process(eth_mclk)
begin
begin
if rising_edge(eth_mclk) then
tx_start_0 <= tx_start;
tx_start_1 <= tx_start_0;
case tx_state is
when header =>
txd <= eth_packet(to_integer(tx_cnt(6 downto 0)));
tx_en <= '1';
if tx_cnt < 41 then
tx_cnt <= tx_cnt + 1;
else
tx_cnt <= (others => '0');
tx_state <= data;
end if;
when data =>
txd <= sample_ram(to_integer(tx_cnt));
tx_en <= '1';
tx_cnt <= tx_cnt + 1;
if tx_cnt = 8191 then
tx_state <= idle;
tx_cnt <= (others => '0');
end if;
when others => -- State = idle
txd <= (others => '0');
tx_en <= '0';
if tx_start_1 = '1' then
tx_state <= header;
end if;
end case;
tx_start_0 <= tx_start;
tx_start_1 <= tx_start_0;
case tx_state is
when header =>
txd <= eth_packet(to_integer(tx_cnt(6 downto 0)));
tx_en <= '1';
if tx_cnt < 41 then
tx_cnt <= tx_cnt + 1;
else
tx_cnt <= (others => '0');
tx_state <= data;
end if;
when data =>
txd <= sample_ram(to_integer(tx_cnt));
tx_en <= '1';
tx_cnt <= tx_cnt + 1;
if tx_cnt = 8191 then
tx_state <= idle;
tx_cnt <= (others => '0');
end if;
when others => -- State = idle
txd <= (others => '0');
tx_en <= '0';
if tx_start_1 = '1' then
tx_state <= header;
end if;
end case;
end if;
end process;
end process;
end architecture Behavioral;
end architecture Behavioral;
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment