Commit 5a5eb556 authored by Paul Boven's avatar Paul Boven
Browse files

Using coregen to generate the FFT_stream

parent d5ef3fbd
##############################################################
#
# Xilinx Core Generator version K.39
# Date: Tue Dec 2 21:55:35 2008
# Xilinx Core Generator version 14.7
# Date: Wed Sep 21 20:19:19 2016
#
##############################################################
#
......@@ -12,44 +12,48 @@
#
##############################################################
#
# Generated from component: xilinx.com:ip:xfft:7.0
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET addpads = false
SET asysymbol = false
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET createndf = false
SET designentry = VHDL
SET device = xc3sd1800a
SET devicefamily = spartan3adsp
SET flowvendor = Foundation_iSE
SET formalverification = False
SET foundationsym = False
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fg676
SET removerpms = False
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = True
SET vhdlsim = True
SET verilogsim = false
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT Fast_Fourier_Transform family Xilinx,_Inc. 6.0
SELECT Fast_Fourier_Transform family Xilinx,_Inc. 7.0
# END Select
# BEGIN Parameters
CSET butterfly_type=use_luts
CSET ce=false
CSET channels=1
CSET complex_mult_type=use_mults_resources
CSET component_name=FFT_stream
CSET cyclic_prefix_insertion=false
CSET data_format=fixed_point
CSET fast_butterfly=false
CSET fast_complex_mult=false
CSET implementation_options=pipelined_streaming_io
CSET input_data_offset=no_offset
CSET input_width=16
CSET memory_options_data=block_ram
CSET memory_options_hybrid=true
CSET memory_options_phase_factors=block_ram
CSET memory_options_reorder=block_ram
CSET number_of_stages_using_block_ram_for_data_and_phase_factors=5
CSET optimize_for_speed_using_xtreme_dsp_slices=false
CSET output_ordering=natural_order
CSET ovflo=false
CSET phase_factor_width=16
......@@ -61,6 +65,8 @@ CSET target_clock_frequency=125
CSET target_data_throughput=50
CSET transform_length=4096
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2013-10-13T18:46:09Z
# END Extra information
GENERATE
# CRC: dc5a4490
# CRC: b632f77e
......@@ -8,7 +8,7 @@ all: main.twr main.bit
xst/projnav.tmp:
mkdir -p xst/projnav.tmp
# XST
main.ngc: main.xst main.prj main.vhd FFT_stream.xco eth_tx.vhd PCK_CRC32_D4.vhd LCD_Driver.vhd LCD_Controller.vhd window.vhd main.lso xst/projnav.tmp
main.ngc: main.xst main.prj main.vhd FFT_stream.ngc eth_tx.vhd PCK_CRC32_D4.vhd LCD_Driver.vhd LCD_Controller.vhd window.vhd main.lso xst/projnav.tmp
xst -ifn main.xst -ofn main.syr
# TODO: generate the window file automatically
......@@ -16,6 +16,9 @@ main.ngc: main.xst main.prj main.vhd FFT_stream.xco eth_tx.vhd PCK_CRC32_D4.vhd
#window.vhd: window.pl
# perl window.pl
FFT_stream.ngc: FFT_stream.xco
coregen -b FFT_stream.xco -p main.prj
# Ngdbuild
main.ngd: main.ngc main.ucf
ngdbuild -dd _nog -nt timestamp -p xc3sd1800a-fg676-4 -uc main.ucf main.ngc main.ngd
......
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