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Commit 62078b2e authored by Paul Boven's avatar Paul Boven
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Adding the 70MS/s raw-mode

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VHDL/Makefile
View file @ 62078b2e
......@@ -5,7 +5,7 @@
# http://www.camras.nl/
# http://gitlab.camras.nl/paulb/DT-Backend-S3A1800dsp
SUBDIRS = S3ADC_v03 S3ADC-4k
SUBDIRS = S3ADC_v03 S3ADC-4k S3ADC_1G
SUBCLEAN = $(addsuffix .clean,$(SUBDIRS))
.PHONY: all clean $(SUBDIRS) $(SUBCLEAN)
......
VHDL/S3ADC_1G/CRC32_D16.vhd 0 → 100644
View file @ 62078b2e
--------------------------------------------------------------------------------
-- Copyright (C) 1999-2008 Easics NV.
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains the original copyright notice
-- and the associated disclaimer.
--
-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
--
-- Purpose : synthesizable CRC function
-- * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- * data width: 16
--
-- Info : tools@easics.be
-- http://www.easics.com
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package PCK_CRC32_D16 is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 16
-- convention: the first serial bit is D[15]
function nextCRC32_D16
(Data: std_logic_vector(15 downto 0);
crc: std_logic_vector(31 downto 0))
return std_logic_vector;
end PCK_CRC32_D16;
package body PCK_CRC32_D16 is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 16
-- convention: the first serial bit is D[15]
function nextCRC32_D16
(Data: std_logic_vector(15 downto 0);
crc: std_logic_vector(31 downto 0))
return std_logic_vector is
variable d: std_logic_vector(15 downto 0);
variable c: std_logic_vector(31 downto 0);
variable newcrc: std_logic_vector(31 downto 0);
begin
d := Data;
c := crc;
newcrc(31) := d(3) xor d(5) xor d(6) xor d(9) xor d(15) xor c(15) xor c(9) xor c(6) xor c(5) xor c(3);
newcrc(30) := d(2) xor d(3) xor d(4) xor d(6) xor d(8) xor d(9) xor d(14) xor d(15) xor c(15) xor c(14) xor c(9) xor c(8) xor c(6) xor c(4) xor c(3) xor c(2);
newcrc(29) := d(1) xor d(2) xor d(6) xor d(7) xor d(8) xor d(9) xor d(13) xor d(14) xor d(15) xor c(15) xor c(14) xor c(13) xor c(9) xor c(8) xor c(7) xor c(6) xor c(2) xor c(1);
newcrc(28) := d(0) xor d(1) xor d(5) xor d(6) xor d(7) xor d(8) xor d(12) xor d(13) xor d(14) xor c(14) xor c(13) xor c(12) xor c(8) xor c(7) xor c(6) xor c(5) xor c(1) xor c(0);
newcrc(27) := d(0) xor d(3) xor d(4) xor d(7) xor d(9) xor d(11) xor d(12) xor d(13) xor d(15) xor c(15) xor c(13) xor c(12) xor c(11) xor c(9) xor c(7) xor c(4) xor c(3) xor c(0);
newcrc(26) := d(2) xor d(5) xor d(8) xor d(9) xor d(10) xor d(11) xor d(12) xor d(14) xor d(15) xor c(15) xor c(14) xor c(12) xor c(11) xor c(10) xor c(9) xor c(8) xor c(5) xor c(2);
newcrc(25) := d(1) xor d(4) xor d(7) xor d(8) xor d(9) xor d(10) xor d(11) xor d(13) xor d(14) xor c(14) xor c(13) xor c(11) xor c(10) xor c(9) xor c(8) xor c(7) xor c(4) xor c(1);
newcrc(24) := d(0) xor d(5) xor d(7) xor d(8) xor d(10) xor d(12) xor d(13) xor d(15) xor c(15) xor c(13) xor c(12) xor c(10) xor c(8) xor c(7) xor c(5) xor c(0);
newcrc(23) := d(3) xor d(4) xor d(5) xor d(7) xor d(11) xor d(12) xor d(14) xor d(15) xor c(15) xor c(14) xor c(12) xor c(11) xor c(7) xor c(5) xor c(4) xor c(3);
newcrc(22) := d(2) xor d(3) xor d(4) xor d(6) xor d(10) xor d(11) xor d(13) xor d(14) xor c(14) xor c(13) xor c(11) xor c(10) xor c(6) xor c(4) xor c(3) xor c(2);
newcrc(21) := d(1) xor d(2) xor d(6) xor d(10) xor d(12) xor d(13) xor d(15) xor c(15) xor c(13) xor c(12) xor c(10) xor c(6) xor c(2) xor c(1);
newcrc(20) := d(0) xor d(1) xor d(3) xor d(6) xor d(11) xor d(12) xor d(14) xor d(15) xor c(15) xor c(14) xor c(12) xor c(11) xor c(6) xor c(3) xor c(1) xor c(0);
newcrc(19) := d(0) xor d(2) xor d(3) xor d(6) xor d(9) xor d(10) xor d(11) xor d(13) xor d(14) xor d(15) xor c(15) xor c(14) xor c(13) xor c(11) xor c(10) xor c(9) xor c(6) xor c(3) xor c(2) xor c(0);
newcrc(18) := d(1) xor d(2) xor d(5) xor d(8) xor d(9) xor d(10) xor d(12) xor d(13) xor d(14) xor c(14) xor c(13) xor c(12) xor c(10) xor c(9) xor c(8) xor c(5) xor c(2) xor c(1);
newcrc(17) := d(0) xor d(1) xor d(4) xor d(7) xor d(8) xor d(9) xor d(11) xor d(12) xor d(13) xor c(13) xor c(12) xor c(11) xor c(9) xor c(8) xor c(7) xor c(4) xor c(1) xor c(0);
newcrc(16) := d(0) xor d(3) xor d(6) xor d(7) xor d(8) xor d(10) xor d(11) xor d(12) xor c(12) xor c(11) xor c(10) xor c(8) xor c(7) xor c(6) xor c(3) xor c(0);
newcrc(15) := d(2) xor d(3) xor d(7) xor d(10) xor d(11) xor d(15) xor c(31) xor c(15) xor c(11) xor c(10) xor c(7) xor c(3) xor c(2);
newcrc(14) := d(1) xor d(2) xor d(6) xor d(9) xor d(10) xor d(14) xor c(30) xor c(14) xor c(10) xor c(9) xor c(6) xor c(2) xor c(1);
newcrc(13) := d(0) xor d(1) xor d(5) xor d(8) xor d(9) xor d(13) xor c(29) xor c(13) xor c(9) xor c(8) xor c(5) xor c(1) xor c(0);
newcrc(12) := d(0) xor d(4) xor d(7) xor d(8) xor d(12) xor c(28) xor c(12) xor c(8) xor c(7) xor c(4) xor c(0);
newcrc(11) := d(3) xor d(6) xor d(7) xor d(11) xor c(27) xor c(11) xor c(7) xor c(6) xor c(3);
newcrc(10) := d(2) xor d(5) xor d(6) xor d(10) xor c(26) xor c(10) xor c(6) xor c(5) xor c(2);
newcrc(9) := d(1) xor d(3) xor d(4) xor d(6) xor d(15) xor c(25) xor c(15) xor c(6) xor c(4) xor c(3) xor c(1);
newcrc(8) := d(0) xor d(2) xor d(6) xor d(9) xor d(14) xor d(15) xor c(24) xor c(15) xor c(14) xor c(9) xor c(6) xor c(2) xor c(0);
newcrc(7) := d(1) xor d(5) xor d(8) xor d(13) xor d(14) xor c(23) xor c(14) xor c(13) xor c(8) xor c(5) xor c(1);
newcrc(6) := d(0) xor d(4) xor d(7) xor d(12) xor d(13) xor c(22) xor c(13) xor c(12) xor c(7) xor c(4) xor c(0);
newcrc(5) := d(5) xor d(9) xor d(11) xor d(12) xor d(15) xor c(21) xor c(15) xor c(12) xor c(11) xor c(9) xor c(5);
newcrc(4) := d(4) xor d(8) xor d(10) xor d(11) xor d(14) xor c(20) xor c(14) xor c(11) xor c(10) xor c(8) xor c(4);
newcrc(3) := d(3) xor d(7) xor d(9) xor d(10) xor d(13) xor c(19) xor c(13) xor c(10) xor c(9) xor c(7) xor c(3);
newcrc(2) := d(2) xor d(6) xor d(8) xor d(9) xor d(12) xor c(18) xor c(12) xor c(9) xor c(8) xor c(6) xor c(2);
newcrc(1) := d(1) xor d(5) xor d(7) xor d(8) xor d(11) xor c(17) xor c(11) xor c(8) xor c(7) xor c(5) xor c(1);
newcrc(0) := d(0) xor d(4) xor d(6) xor d(7) xor d(10) xor c(16) xor c(10) xor c(7) xor c(6) xor c(4) xor c(0);
return newcrc;
end nextCRC32_D16;
end PCK_CRC32_D16;
VHDL/S3ADC_1G/CRC32_D8.vhd 0 → 100644
View file @ 62078b2e
--------------------------------------------------------------------------------
-- Copyright (C) 1999-2008 Easics NV.
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains the original copyright notice
-- and the associated disclaimer.
--
-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
--
-- Purpose : synthesizable CRC function
-- * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- * data width: 8
--
-- Info : tools@easics.be
-- http://www.easics.com
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package pck_crc32_d8 is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial bit is D[7]
function nextCRC32_D8
(Data: std_logic_vector(7 downto 0);
crc: std_logic_vector(31 downto 0))
return std_logic_vector;
end pck_crc32_d8;
package body pck_crc32_d8 is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial bit is D[7]
function nextCRC32_D8
(Data: std_logic_vector(7 downto 0);
crc: std_logic_vector(31 downto 0))
return std_logic_vector is
variable d: std_logic_vector(7 downto 0);
variable c: std_logic_vector(31 downto 0);
variable newcrc: std_logic_vector(31 downto 0);
begin
d := Data;
c := crc;
newcrc(31) := d(1) xor d(7) xor c(7) xor c(1);
newcrc(30) := d(0) xor d(1) xor d(6) xor d(7) xor c(7) xor c(6) xor c(1) xor c(0);
newcrc(29) := d(0) xor d(1) xor d(5) xor d(6) xor d(7) xor c(7) xor c(6) xor c(5) xor c(1) xor c(0);
newcrc(28) := d(0) xor d(4) xor d(5) xor d(6) xor c(6) xor c(5) xor c(4) xor c(0);
newcrc(27) := d(1) xor d(3) xor d(4) xor d(5) xor d(7) xor c(7) xor c(5) xor c(4) xor c(3) xor c(1);
newcrc(26) := d(0) xor d(1) xor d(2) xor d(3) xor d(4) xor d(6) xor d(7) xor c(7) xor c(6) xor c(4) xor c(3) xor c(2) xor c(1) xor c(0);
newcrc(25) := d(0) xor d(1) xor d(2) xor d(3) xor d(5) xor d(6) xor c(6) xor c(5) xor c(3) xor c(2) xor c(1) xor c(0);
newcrc(24) := d(0) xor d(2) xor d(4) xor d(5) xor d(7) xor c(7) xor c(5) xor c(4) xor c(2) xor c(0);
newcrc(23) := d(3) xor d(4) xor d(6) xor d(7) xor c(31) xor c(7) xor c(6) xor c(4) xor c(3);
newcrc(22) := d(2) xor d(3) xor d(5) xor d(6) xor c(30) xor c(6) xor c(5) xor c(3) xor c(2);
newcrc(21) := d(2) xor d(4) xor d(5) xor d(7) xor c(29) xor c(7) xor c(5) xor c(4) xor c(2);
newcrc(20) := d(3) xor d(4) xor d(6) xor d(7) xor c(28) xor c(7) xor c(6) xor c(4) xor c(3);
newcrc(19) := d(1) xor d(2) xor d(3) xor d(5) xor d(6) xor d(7) xor c(27) xor c(7) xor c(6) xor c(5) xor c(3) xor c(2) xor c(1);
newcrc(18) := d(0) xor d(1) xor d(2) xor d(4) xor d(5) xor d(6) xor c(26) xor c(6) xor c(5) xor c(4) xor c(2) xor c(1) xor c(0);
newcrc(17) := d(0) xor d(1) xor d(3) xor d(4) xor d(5) xor c(25) xor c(5) xor c(4) xor c(3) xor c(1) xor c(0);
newcrc(16) := d(0) xor d(2) xor d(3) xor d(4) xor c(24) xor c(4) xor c(3) xor c(2) xor c(0);
newcrc(15) := d(2) xor d(3) xor d(7) xor c(23) xor c(7) xor c(3) xor c(2);
newcrc(14) := d(1) xor d(2) xor d(6) xor c(22) xor c(6) xor c(2) xor c(1);
newcrc(13) := d(0) xor d(1) xor d(5) xor c(21) xor c(5) xor c(1) xor c(0);
newcrc(12) := d(0) xor d(4) xor c(20) xor c(4) xor c(0);
newcrc(11) := d(3) xor c(19) xor c(3);
newcrc(10) := d(2) xor c(18) xor c(2);
newcrc(9) := d(7) xor c(17) xor c(7);
newcrc(8) := d(1) xor d(6) xor d(7) xor c(16) xor c(7) xor c(6) xor c(1);
newcrc(7) := d(0) xor d(5) xor d(6) xor c(15) xor c(6) xor c(5) xor c(0);
newcrc(6) := d(4) xor d(5) xor c(14) xor c(5) xor c(4);
newcrc(5) := d(1) xor d(3) xor d(4) xor d(7) xor c(13) xor c(7) xor c(4) xor c(3) xor c(1);
newcrc(4) := d(0) xor d(2) xor d(3) xor d(6) xor c(12) xor c(6) xor c(3) xor c(2) xor c(0);
newcrc(3) := d(1) xor d(2) xor d(5) xor c(11) xor c(5) xor c(2) xor c(1);
newcrc(2) := d(0) xor d(1) xor d(4) xor c(10) xor c(4) xor c(1) xor c(0);
newcrc(1) := d(0) xor d(3) xor c(9) xor c(3) xor c(0);
newcrc(0) := d(2) xor c(8) xor c(2);
return newcrc;
end nextCRC32_D8;
end pck_crc32_d8;
VHDL/S3ADC_1G/LCD_Controller.vhd 0 → 100644
View file @ 62078b2e
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name: LCD_Controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- $Id: LCD_Controller.vhd,v 1.2 2012/01/15 01:46:16 paul Exp paul $
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity LCD_Controller is
Port ( clk : in STD_LOGIC;
START: in STD_LOGIC;
DONE: out STD_LOGIC;
RS: in STD_LOGIC;
DATA: in STD_LOGIC_VECTOR(7 downto 0);
LCD_RS : out STD_LOGIC;
LCD_RW : out STD_LOGIC;
LCD_Data : out STD_LOGIC_VECTOR (7 downto 4);
LCD_E : out STD_LOGIC);
end;
architecture Behavioral of LCD_Controller is
type statetype is (Init, Init2, Setup, Enable, Hold);
signal state: statetype := Init;
signal counter: unsigned(12 downto 0) := (others => '0');
signal nybble: STD_LOGIC := '1';
signal low_nybble: STD_LOGIC_VECTOR(3 downto 0);
signal high_nybble: STD_LOGIC_VECTOR(3 downto 0);
signal rs_reg: STD_LOGIC := '0';
begin -- Behavioral
-- A state machine to generate timing signals for an 44780 compatible LCD controller.
-- It uses a simplified timing diagram where data and RS are sampled at START and
-- sent to the LCD, then after a setup time of 60ns, Enable is activated.
-- After 240ns of enable time, it is lowered again. Although hold-time only needs to be 10ns,
-- it is stretched to 200ns so the 500ns cycle time of Enable can be met.
-- By using the same countdown counter for all states, and comparing with zero,
-- only one counter and one comparator will be instantiated, keeping this small.
process (clk) begin
if rising_edge(clk) then
if state = Init and nybble = '1' and START = '1' then
-- Register LCD data and RS bit, then go to Setup
low_nybble <= DATA(3 downto 0);
high_nybble <= DATA(7 downto 4);
rs_reg <= RS;
counter <= to_unsigned(3,counter'length); -- 60ns, setup time
state <= Setup;
elsif state = Init2 then
counter <= to_unsigned(3,counter'length); -- 60ns, setup again
state <= Setup;
elsif state = Setup then
-- Wait for setup time before Enable goes high
if counter = 0 then
counter <= to_unsigned(12,counter'length); -- 240ns, enable high
state <= Enable;
else
counter <= counter - 1;
end if;
elsif state = Enable then
-- Assert Enable and wait for minimun time
if counter = 0 then
counter <= to_unsigned(10,counter'length); -- 200ns, hold time
state <= Hold;
else
counter <= counter - 1;
end if;
elsif state = Hold then
-- Hold data, redo for the second half of the nybble
if counter = 0 then
if nybble = '1' then
state <= Init2;
nybble <= '0';
else
state <= Init;
nybble <= '1';
end if;
else
counter <= counter - 1;
end if;
end if;
end if;
end process;
LCD_Data(7 downto 4) <= high_nybble when (nybble = '1') else low_nybble;
LCD_RS <= rs_reg;
LCD_E <= '1' when (state = Enable) else '0';
DONE <= '1' when (state = Init) else '0';
LCD_RW <= '0';
end behavioral;
VHDL/S3ADC_1G/LCD_Driver.vhd 0 → 100644
View file @ 62078b2e
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name: LCD_Controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- $Id: LCD_Driver.vhd,v 1.3 2012/01/30 20:32:56 paulb Exp paulb $
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity LCD_Driver is
Generic (TN: integer := 6);
Port ( Clk : in STD_LOGIC;
LCD_RS : out STD_LOGIC;
LCD_RW : out STD_LOGIC;
LCD_Data : out STD_LOGIC_VECTOR (7 downto 4);
clk_1hz: in STD_LOGIC;
LCD_E : out STD_LOGIC);
end LCD_Driver;
architecture Behavioral of LCD_Driver is
signal done: STD_LOGIC;
signal start: STD_LOGIC;
signal textcounter: unsigned(TN-1 downto 0) := (others => '0');
type text_type is array(0 to 2**TN-1) of STD_LOGIC_VECTOR(8 downto 0);
constant text_block: text_type := (
"0" & "00101000", -- Initialize
"0" & "00101000", -- Initialize
"0" & "00101000", -- Initialize: 4 bit, 2 line, 5*7
"0" & "00001100", -- Display on, cursor off, blink off
"0" & "00000001", -- Clear display
"0" & "01001000", -- CGram first character: create a "\"
"1" & "00000000", -- A cgram entry
"1" & "00010000", -- A cgram entry
"1" & "00001000", -- A cgram entry
"1" & "00000100", -- A cgram entry
"1" & "00000010", -- A cgram entry
"1" & "00000001", -- A cgram entry
"1" & "00000000", -- A cgram entry
"1" & "00000000", -- A cgram entry
"0" & "10000000", -- Home cursors, DDram 15
"1" & std_logic_vector(to_unsigned(character'pos('A'),8)), -- 16
"1" & std_logic_vector(to_unsigned(character'pos('D'),8)), -- 17
"1" & std_logic_vector(to_unsigned(character'pos('C'),8)), -- 18
"1" & std_logic_vector(to_unsigned(character'pos(' '),8)), -- 19
"1" & std_logic_vector(to_unsigned(character'pos('M'),8)), -- 20
"1" & std_logic_vector(to_unsigned(character'pos('o'),8)), -- 21
"1" & std_logic_vector(to_unsigned(character'pos('d'),8)), -- 22
"1" & std_logic_vector(to_unsigned(character'pos('e'),8)), -- 23
"1" & std_logic_vector(to_unsigned(character'pos(' '),8)), -- 24
"1" & std_logic_vector(to_unsigned(character'pos(' '),8)), -- 25
"1" & std_logic_vector(to_unsigned(character'pos(' '),8)), -- 26
"1" & x"20", -- (space) -- 27
"1" & std_logic_vector(to_unsigned(character'pos('v'),8)), -- 28
"1" & std_logic_vector(to_unsigned(character'pos('0'),8)), -- 29
"1" & std_logic_vector(to_unsigned(character'pos('.'),8)), -- 30
"1" & std_logic_vector(to_unsigned(character'pos('1'),8)), -- 31
"0" & "11000000", -- Newline
"1" & std_logic_vector(to_unsigned(character'pos('1'),8)), -- 33
"1" & std_logic_vector(to_unsigned(character'pos('G'),8)), -- 34
"1" & std_logic_vector(to_unsigned(character'pos('b'),8)), -- 35
"1" & std_logic_vector(to_unsigned(character'pos('/'),8)), -- 36
"1" & std_logic_vector(to_unsigned(character'pos('s'),8)), -- 37
"1" & std_logic_vector(to_unsigned(character'pos(' '),8)), -- 38
"1" & std_logic_vector(to_unsigned(character'pos(' '),8)), -- 39
"1" & x"20", -- (space) -- 40
"1" & std_logic_vector(to_unsigned(character'pos('1'),8)), -- 41
"1" & std_logic_vector(to_unsigned(character'pos('4'),8)), -- 42
"1" & std_logic_vector(to_unsigned(character'pos('0'),8)), -- 43
"1" & std_logic_vector(to_unsigned(character'pos('M'),8)), -- 44
"1" & std_logic_vector(to_unsigned(character'pos('H'),8)), -- 45
"1" & std_logic_vector(to_unsigned(character'pos('z'),8)), -- 46
"0" & "11001111", -- Last display pos
"1" & x"23"); -- #
signal text_block_buffer: STD_LOGIC_VECTOR(8 downto 0);
signal data: STD_LOGIC_VECTOR(7 downto 0);
signal rs: STD_LOGIC;
signal delay: unsigned(24 downto 0) := (others => '1');
signal spinner: unsigned(1 downto 0) := (others => '0');
type statetype is (Init, Delaying, Running);
signal state: statetype := Init;
signal clk_1hz_0: std_logic := '0';
signal clk_1hz_1: std_logic := '0';
signal clk_1hz_2: std_logic := '0';
component LCD_Controller
Port ( clk : std_logic;
START: in STD_LOGIC;
DONE: out STD_LOGIC;
RS: in STD_LOGIC;
DATA: in STD_LOGIC_VECTOR(7 downto 0);
LCD_RS : out STD_LOGIC;
LCD_RW : out STD_LOGIC;
LCD_Data : out STD_LOGIC_VECTOR (7 downto 4);
LCD_E : out STD_LOGIC);
end component;
begin -- Behavioral
LCD_Controller_1: LCD_controller
port map( clk => clk,
DONE => DONE,
START => START,
DATA => DATA,
RS => RS,
LCD_DATA => LCD_DATA,
LCD_RW => LCD_RW,
LCD_E => LCD_E,
LCD_RS => LCD_RS);
data <= text_block_buffer(7 downto 0);
rs <= text_block_buffer(8);
process (clk) begin
if rising_edge(clk) then
clk_1hz_0 <= clk_1hz;
clk_1hz_1 <= clk_1hz_0;
clk_1hz_2 <= clk_1hz_1;
if clk_1hz_2 = not clk_1hz_1 then
spinner <= spinner + 1;
end if; -- clk_1hz_2 = not clk_hz_1
if state = Init then
if DONE = '1' then
state <= Delaying;
end if;
elsif state = Delaying then
if delay > 0 then
delay <= delay - 1;
else
state <= Running;
delay <= to_unsigned(386265,delay'length); -- 15ms
end if;
elsif state = Running then
state <= Init;
if textcounter = 47 then
textcounter <= to_unsigned(46,textcounter'length);
case spinner is
when "00" => text_block_buffer <=
"1" & std_logic_vector(to_unsigned(character'pos('-'),8)); -- 48
when "01" => text_block_buffer <=
"1" & "00000001"; -- Special character, "\" from cgram
when "10" => text_block_buffer <=
"1" & std_logic_vector(to_unsigned(character'pos('|'),8)); -- 52
when others => text_block_buffer <=
"1" & std_logic_vector(to_unsigned(character'pos('/'),8)); -- 54
end case;
else -- textcounter = 47
textcounter <= textcounter + 1;
text_block_buffer <= text_block(to_integer(textcounter));
end if; -- textcounter = 47
end if; -- State
end if; -- rising_edge(clk)
end process;
START <= '1' when (state = Running) else '0';
end Behavioral;
VHDL/S3ADC_1G/Makefile 0 → 100644
View file @ 62078b2e
# A Makefile to drive the Xilinx tools.
# This project reads 70MS/s data from a 10bit A/D,
# and sends it out over the 1Gb/s ethernet
# $Id: Makefile,v 1.1 2012/01/03 21:00:36 paul Exp paul $
all: main.twr main.bit raw.bit
clean:
rm -rf raw.bit main.bit main.twr main.bgn main.bld main.cgc main.cgp main.drc main.ncd main.ngc main.ngd main.ngr main.pad main.par main.pcf man.twx main.syr main.twr main.twx main.unroutes main.xpi .lso main.ptwx main_bitgen.xwbt main_map.map main_map.mrp main_map.ncd main_map.ngm main_map.xrpt main_ngdbuild.xrpt main_pad.csv main_pad.txt main_par.xrpt main_summary.xml main_usage.xml main_xst.xrpt tmp/ _nog/ _xmsgs/ usage_statistics_webtalk.html webtalk.log xlnx_auto_0_xdb xst/
xst/projnav.tmp:
mkdir -p xst/projnav.tmp
# XST
main.ngc: main.xst main.prj main.vhd LCD_Driver.vhd LCD_Controller.vhd xst/projnav.tmp
xst -ifn main.xst -ofn main.syr
# Ngdbuild
main.ngd: main.ngc main.ucf
ngdbuild -dd _nog -nt timestamp -p xc3sd1800a-fg676-4 -uc main.ucf main.ngc main.ngd
# Map
main.pcf: main.ngd
map -p xc3sd1800a-fg676-4 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
# PAR
main.ncd: main.pcf
par -w -ol std -t 1 main_map.ncd main.ncd main.pcf
# Timing Report
main.twr: main.ucf main.ncd
trce -v 3 -s 4 main.ncd -o main.twr main.pcf -ucf main.ucf
# Bitgen
main.bit: main.ut main.ncd
bitgen -f main.ut main.ncd
# Public name
raw.bit: main.bit
cp main.bit raw.bit
VHDL/S3ADC_1G/eth_tx_mac.vhd 0 → 100644
View file @ 62078b2e
----------------------------------------------------------------------------------
-- Company: CAMRAS
-- Engineer: Paul Boven
--
-- Create Date: 2012-01-02
-- Design Name: S3ADC_1G
-- Module Name: main - Behavioral
-- Project Name:
-- Target Devices: S3 DSP 1800
-- Tool versions: 13.3
-- Description:
--
-- Dependencies:
--
-- $Id: eth_tx_mac.vhd,v 1.2 2012/01/23 01:01:50 paul Exp paulb $
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.pck_crc32_d16.ALL;
use work.pck_crc32_d8.ALL;
entity eth_tx_mac is
Port ( clk : in STD_LOGIC;
input: in STD_LOGIC_VECTOR(7 downto 0);
output: out STD_LOGIC_VECTOR(7 downto 0);
tx_en_in: in STD_LOGIC;
tx_en_out: out STD_LOGIC); -- all data received, start outputting CRC
end eth_tx_mac;
architecture Behavioral of eth_tx_mac is
signal crc: std_logic_vector(31 downto 0);
type state_type is (Idle, Preamble, Data, Drain, CRC_out);
signal state: state_type := Idle;
signal cnt: unsigned(2 downto 0);
signal length_odd: std_logic;
signal d9: std_logic_vector(7 downto 0);
signal d8: std_logic_vector(7 downto 0);
signal d7: std_logic_vector(7 downto 0);
signal d6: std_logic_vector(7 downto 0);
signal d5: std_logic_vector(7 downto 0);
signal d4: std_logic_vector(7 downto 0);
signal d3: std_logic_vector(7 downto 0);
signal d2: std_logic_vector(7 downto 0);
signal d1: std_logic_vector(7 downto 0);
begin process(clk)
begin
if rising_edge(clk) then
-- Input pipeline: delay by 8 bytes becaus