Commit 756544f9 authored by Paul Boven's avatar Paul Boven
Browse files

First working SDR version. Renamed signal idx to lo, fixed remaining bugs....

First working SDR version. Renamed signal idx to lo, fixed remaining bugs. TODO: better filter (in terms of resource requirements and flatness).
parent 32b0eb9c
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Wed Dec 14 19:32:22 2016
# Date: Thu Dec 15 21:27:47 2016
#
##############################################################
#
......@@ -28,10 +28,10 @@ SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fg676
SET package = cs484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET speedgrade = -5
SET verilogsim = false
SET vhdlsim = true
# END Project Options
......@@ -44,16 +44,16 @@ CSET bestprecision=false
CSET chan_in_adv=0
CSET clock_frequency=140
CSET coefficient_buffer_type=Automatic
CSET coefficient_file=no_coe_file_loaded
CSET coefficient_fractional_bits=0
CSET coefficient_file=./fir_filter.coe
CSET coefficient_fractional_bits=18
CSET coefficient_reload=false
CSET coefficient_sets=1
CSET coefficient_sign=Signed
CSET coefficient_structure=Inferred
CSET coefficient_width=16
CSET coefficientsource=Vector
CSET coefficientsource=COE_File
CSET coefficientvector=6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6
CSET columnconfig=1
CSET columnconfig=8
CSET component_name=fir_compiler_v5_0
CSET data_buffer_type=Automatic
CSET data_fractional_bits=0
......@@ -80,10 +80,10 @@ CSET optimization_goal=Speed
CSET output_buffer_type=Automatic
CSET output_rounding_mode=Truncate_LSBs
CSET output_width=16
CSET passband_max=0.5
CSET passband_max=0.4
CSET passband_min=0.0
CSET preference_for_other_storage=Automatic
CSET quantization=Integer_Coefficients
CSET quantization=Maximize_Dynamic_Range
CSET rate_change_type=Integer
CSET ratespecification=Frequency_Specification
CSET registered_output=true
......@@ -91,7 +91,7 @@ CSET sample_frequency=70
CSET sampleperiod=1
CSET sclr_deterministic=false
CSET stopband_max=1.0
CSET stopband_min=0.5
CSET stopband_min=0.6
CSET usechan_in_adv=false
CSET zero_pack_factor=1
# END Parameters
......@@ -99,4 +99,4 @@ CSET zero_pack_factor=1
MISC pkg_timestamp=2013-10-13T18:46:09Z
# END Extra information
GENERATE
# CRC: 84f03bf4
# CRC: 8fb41bbc
radix=10;
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......@@ -27,7 +27,7 @@ use IEEE.NUMERIC_STD.ALL;
--use UNISIM.VComponents.all;
entity lo_block is
Port ( idx : in unsigned (8 downto 0);
Port ( lo : in unsigned (8 downto 0);
lo_I : out signed (15 downto 0);
lo_Q : out signed (15 downto 0);
clk : in STD_LOGIC);
......@@ -170,14 +170,14 @@ x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000",
x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000"
);
signal idx_buf: unsigned(8 downto 0);
signal lo_buf: unsigned(8 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
idx_buf <= idx;
lo_I <= lo_rom_I(to_integer(idx_buf));
lo_Q <= lo_rom_Q(to_integer(idx_buf));
lo_buf <= lo;
lo_I <= lo_rom_I(to_integer(lo_buf));
lo_Q <= lo_rom_Q(to_integer(lo_buf));
end if;
end process;
end Behavioral;
......
......@@ -27,7 +27,7 @@ use IEEE.NUMERIC_STD.ALL;
--use UNISIM.VComponents.all;
entity lo_block is
Port ( idx : in unsigned (8 downto 0);
Port ( lo : in unsigned (8 downto 0);
lo_I : out signed (15 downto 0);
lo_Q : out signed (15 downto 0);
clk : in STD_LOGIC);
......@@ -44,14 +44,14 @@ architecture Behavioral of lo_block is
-- TABLE GOES HERE --
);
signal idx_buf: unsigned(8 downto 0);
signal lo_buf: unsigned(8 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
idx_buf <= idx;
lo_I <= lo_rom_I(to_integer(idx_buf));
lo_Q <= lo_rom_Q(to_integer(idx_buf));
lo_buf <= lo;
lo_I <= lo_rom_I(to_integer(lo_buf));
lo_Q <= lo_rom_Q(to_integer(lo_buf));
end if;
end process;
end Behavioral;
......
......@@ -70,7 +70,7 @@ signal lo_I: signed(15 downto 0);
signal lo_Q: signed(15 downto 0);
signal lo_I_buf: signed(15 downto 0);
signal lo_Q_buf: signed(15 downto 0);
signal idx: unsigned(8 downto 0) := (others => '0');
signal lo: unsigned(8 downto 0) := (others => '0');
signal rfd_I: STD_LOGIC;
signal rdy_I: STD_LOGIC;
signal rfd_Q: STD_LOGIC;
......@@ -136,7 +136,7 @@ port map(clk => LCD_CLK,
lo_block: entity work.lo_block
port map(clk => clk,
idx => idx,
lo => lo,
lo_I => lo_I,
lo_Q => lo_Q);
......@@ -183,8 +183,8 @@ process(clk)
adc_clk_sig <= not adc_clk_sig;
sample_ram(to_integer(pkt_idx_buf)) <= ram_buf;
pkt_idx_buf <= pkt_idx;
din_I <= std_logic_vector(resize(buf_I_buf,16));
din_Q <= std_logic_vector(resize(buf_Q_buf,16));
din_I <= std_logic_vector(buf_I_buf(25 downto 10));
din_Q <= std_logic_vector(buf_Q_buf(25 downto 10));
buf_I_buf <= buf_I;
buf_Q_buf <= buf_Q;
buf_I <= sample_buf2 * lo_I_buf;
......@@ -194,18 +194,17 @@ process(clk)
sample_buf2 <= sample_buf;
if(adc_clk_sig = '1') then
sample_buf <= resize(signed('0' & adc_a) -512, 10);
if idx < 700 then
idx <= idx + 1;
if lo < 349 then
lo <= lo + 1;
else
idx <= (others => '0');
lo <= (others => '0');
end if;
end if;
if(rdy_I = '1') then -- buffer the 16 bit FIR outputs
fir_I_buf <= dout_I;
fir_Q_buf <= dout_Q;
interleave <= lsb_I;
end if;
if interleave = lsb_I then
elsif interleave = lsb_I then
ram_buf <= fir_I_buf(7 downto 0);
interleave <= msb_I;
pkt_idx <= pkt_idx + 1;
......
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