Commit b9b457a3 authored by Paul Boven's avatar Paul Boven
Browse files

Added the pulsar mode VHDL files

parent cf0c31a6
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Mon Oct 10 09:59:13 2016
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:xfft:7.0
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = false
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc3sd1800a
SET devicefamily = spartan3adsp
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fg676
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = false
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT Fast_Fourier_Transform family Xilinx,_Inc. 7.0
# END Select
# BEGIN Parameters
CSET butterfly_type=use_luts
CSET ce=false
CSET channels=1
CSET complex_mult_type=use_mults_resources
CSET component_name=FFT_stream
CSET cyclic_prefix_insertion=false
CSET data_format=fixed_point
CSET implementation_options=pipelined_streaming_io
CSET input_data_offset=no_offset
CSET input_width=16
CSET memory_options_data=block_ram
CSET memory_options_hybrid=false
CSET memory_options_phase_factors=block_ram
CSET memory_options_reorder=block_ram
CSET number_of_stages_using_block_ram_for_data_and_phase_factors=2
CSET output_ordering=natural_order
CSET ovflo=false
CSET phase_factor_width=16
CSET rounding_modes=truncation
CSET run_time_configurable_transform_length=false
CSET scaling_options=unscaled
CSET sclr=false
CSET target_clock_frequency=125
CSET target_data_throughput=50
CSET transform_length=512
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2013-10-13T18:46:09Z
# END Extra information
GENERATE
# CRC: 7b31e7b
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name: LCD_Controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- A fist stab at controlling an LCD (44780 compatible) display via the FPGA.
-- This is written for a Digilent Spartan-3 kit, clocked at 50MHz.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity LCD_Driver is
Generic (TN: integer := 6);
Port ( Clk : in STD_LOGIC;
-- LED: out STD_LOGIC;
-- BT0: in STD_LOGIC;
-- BT1: in STD_LOGIC;
LCD_RS : out STD_LOGIC;
LCD_RW : out STD_LOGIC;
LCD_Data : out STD_LOGIC_VECTOR (7 downto 4);
clk_1hz: in STD_LOGIC;
LCD_E : out STD_LOGIC);
end LCD_Driver;
-- A simple debouncer: press and release BT0 to arm the circuit,
-- Then press BT1 to send a single START pulse to the LCD controller.
-- Release both buttons before arming the circuit again.
-- Led zero shows when the circuit is armed.
architecture Behavioral of LCD_Driver is
type debouncetype is (Ready, Armed, Active, Disarmed);
signal debounce: debouncetype := Disarmed;
signal done: STD_LOGIC;
signal start: STD_LOGIC;
signal textcounter: unsigned(TN-1 downto 0) := (others => '0');
type text_type is array(0 to 2**TN-1) of STD_LOGIC_VECTOR(8 downto 0);
constant text_block: text_type := (
"0" & "00101000", -- Initialize
"0" & "00101000", -- Initialize
"0" & "00101000", -- Initialize: 4 bit, 2 line, 5*7
"0" & "00001100", -- Display on, cursor off, blink off
"0" & "00000001", -- Clear display
"0" & "01001000", -- CGram first character: create a "\"
"1" & "00000000", -- A cgram entry
"1" & "00010000", -- A cgram entry
"1" & "00001000", -- A cgram entry
"1" & "00000100", -- A cgram entry
"1" & "00000010", -- A cgram entry
"1" & "00000001", -- A cgram entry
"1" & "00000000", -- A cgram entry
"1" & "00000000", -- A cgram entry
"0" & "10000000", -- Home cursors, DDram 15
"1" & std_logic_vector(to_unsigned(character'pos('P'),8)), -- 16
"1" & std_logic_vector(to_unsigned(character'pos('u'),8)), -- 17
"1" & std_logic_vector(to_unsigned(character'pos('l'),8)), -- 18
"1" & std_logic_vector(to_unsigned(character'pos('s'),8)), -- 19
"1" & std_logic_vector(to_unsigned(character'pos('a'),8)), -- 20
"1" & std_logic_vector(to_unsigned(character'pos('r'),8)), -- 21
"1" & x"20", -- (space) -- 22
"1" & std_logic_vector(to_unsigned(character'pos('M'),8)), -- 23
"1" & std_logic_vector(to_unsigned(character'pos('o'),8)), -- 24
"1" & std_logic_vector(to_unsigned(character'pos('d'),8)), -- 25
"1" & std_logic_vector(to_unsigned(character'pos('e'),8)), -- 26
"1" & x"20", -- (space) -- 27
"1" & std_logic_vector(to_unsigned(character'pos('v'),8)), -- 28
"1" & std_logic_vector(to_unsigned(character'pos('0'),8)), -- 29
"1" & std_logic_vector(to_unsigned(character'pos('.'),8)), -- 30
"1" & std_logic_vector(to_unsigned(character'pos('3'),8)), -- 31
"0" & "11000000", -- Newline
"1" & std_logic_vector(to_unsigned(character'pos('2'),8)), -- 33
"1" & std_logic_vector(to_unsigned(character'pos('5'),8)), -- 34
"1" & std_logic_vector(to_unsigned(character'pos('6'),8)), -- 35
"1" & std_logic_vector(to_unsigned(character'pos('b'),8)), -- 36
"1" & std_logic_vector(to_unsigned(character'pos('i'),8)), -- 37
"1" & std_logic_vector(to_unsigned(character'pos('n'),8)), -- 38
"1" & std_logic_vector(to_unsigned(character'pos('s'),8)), -- 39
"1" & x"20", -- (space) -- 40
"1" & std_logic_vector(to_unsigned(character'pos('1'),8)), -- 41
"1" & std_logic_vector(to_unsigned(character'pos('4'),8)), -- 42
"1" & std_logic_vector(to_unsigned(character'pos('0'),8)), -- 43
"1" & std_logic_vector(to_unsigned(character'pos('M'),8)), -- 44
"1" & std_logic_vector(to_unsigned(character'pos('H'),8)), -- 45
"1" & std_logic_vector(to_unsigned(character'pos('z'),8)), -- 46
"0" & "11001111", -- Last display pos
"1" & x"23"); -- #
signal text_block_buffer: STD_LOGIC_VECTOR(8 downto 0);
signal data: STD_LOGIC_VECTOR(7 downto 0);
signal rs: STD_LOGIC;
signal delay: unsigned(24 downto 0) := (others => '1');
signal spinner: unsigned(1 downto 0) := (others => '0');
signal clk_1hz_prev: std_logic := '0';
component LCD_Controller
Port ( clk : std_logic;
START: in STD_LOGIC;
DONE: out STD_LOGIC;
RS: in STD_LOGIC;
DATA: in STD_LOGIC_VECTOR(7 downto 0);
LCD_RS : out STD_LOGIC;
LCD_RW : out STD_LOGIC;
LCD_Data : out STD_LOGIC_VECTOR (7 downto 4);
LCD_E : out STD_LOGIC);
end component;
begin -- Behavioral
LCD_Controller_1: LCD_controller
port map( clk => clk,
DONE => DONE,
START => START,
DATA => DATA,
RS => RS,
LCD_DATA => LCD_DATA,
LCD_RW => LCD_RW,
LCD_E => LCD_E,
LCD_RS => LCD_RS);
data <= text_block_buffer(7 downto 0);
rs <= text_block_buffer(8);
process (clk) begin
if rising_edge(clk) then
if clk_1hz = not clk_1hz_prev then
spinner <= spinner + 1;
end if;
clk_1hz_prev <= clk_1hz;
if debounce = Ready and DONE = '1' then
debounce <= Active;
elsif debounce = Active then
debounce <= Disarmed;
elsif debounce = Disarmed then
if delay > 0 then
delay <= delay - 1;
else
delay <= to_unsigned(386265,delay'length); -- 15ms
debounce <= Ready;
if textcounter = 47 then
textcounter <= to_unsigned(46,textcounter'length);
case spinner is
when "00" => text_block_buffer <=
"1" & std_logic_vector(to_unsigned(character'pos('-'),8)); -- 48
when "01" => text_block_buffer <=
"1" & "00000001"; -- Special character, "\" from cgram
when "10" => text_block_buffer <=
"1" & std_logic_vector(to_unsigned(character'pos('|'),8)); -- 52
when others => text_block_buffer <=
"1" & std_logic_vector(to_unsigned(character'pos('/'),8)); -- 54
end case;
else
textcounter <= textcounter + 1;
text_block_buffer <= text_block(to_integer(textcounter));
end if;
end if;
end if;
end if;
end process;
START <= '1' when (debounce = Active) else '0';
end Behavioral;
# A Makefile to drive the Xilinx tools.
# This project reads 70MS/s data from a 10bit A/D, then applies a window
# and runs it trough a (coregen) FFT before sending the data out of
# the Ethernet port.
all: main.twr main.bit
clean:
rm -rf main.bit main.twr FFT_stream.gise FFT_stream.ngc FFT_stream.xise FFT_stream_flist.txt FFT_stream_readme.txt FFT_stream_xmdf.tcl coregen.log main.bgn main.bld main.cgc main.cgp main.drc main.ncd main.ngc main.ngd main.ngr main.pad main.par main.pcf man.twx main.syr main.twr main.twx main.unroutes main.xpi .lso main.ptwx main_bitgen.xwbt main_map.map main_map.mrp main_map.ncd main_map.ngm main_map.xrpt main_ngdbuild.xrpt main_pad.csv main_pad.txt main_par.xrpt main_summary.xml main_usage.xml main_xst.xrpt tmp/ _nog/ _xmsgs/ usage_statistics_webtalk.html webtalk.log xlnx_auto_0_xdb xst/
xst/projnav.tmp:
mkdir -p xst/projnav.tmp
# XST
main.ngc: main.xst main.prj main.vhd FFT_stream.ngc eth_tx.vhd ../common/PCK_CRC32_D4.vhd LCD_Driver.vhd ../common/LCD_Controller.vhd
xst -ifn main.xst -ofn main.syr
# Use coregen to generate the FFT block
FFT_stream.ngc: FFT_stream.xco
coregen -b FFT_stream.xco -p main.prj
# Ngdbuild
main.ngd: main.ngc main.ucf
ngdbuild -dd _nog -nt timestamp -p xc3sd1800a-fg676-4 -uc main.ucf main.ngc main.ngd
# Map
main.pcf: main.ngd
map -p xc3sd1800a-fg676-4 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
# PAR
main.ncd: main.pcf
par -w -ol std -t 1 main_map.ncd main.ncd main.pcf
# Timing Report
main.twr: main.ucf main.ncd
trce -v 3 -s 4 main.ncd -o main.twr main.pcf -ucf main.ucf
# Bitgen
main.bit: main.ut main.ncd
bitgen -f main.ut main.ncd
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:38:07 08/10/2008
-- Design Name:
-- Module Name: eth_tx - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use PCK_CRC32_D4.all;
entity eth_tx is
Port ( clk : in STD_LOGIC;
tx_d : out STD_LOGIC_VECTOR (3 downto 0);
tx_en : out STD_LOGIC;
tx_payload: in STD_LOGIC_VECTOR(3 downto 0);
tx_payload_ctr: out STD_LOGIC_VECTOR(12 downto 0);
tx_start: in std_logic);
end eth_tx;
architecture Behavioral of eth_tx is
constant eth_data_len: integer := 4096; -- Number of nibbles
type eth_preamble_type is array(0 to 15) of std_logic_vector(3 downto 0);
constant eth_preamble: eth_preamble_type := (
-- Preamble + SFD
x"5",x"5", x"5",x"5", x"5",x"5", x"5",x"5", x"5",x"5", x"5",x"5", x"5",x"5", x"D",x"5");
-- Header (Ether (14), IP (20) , UDP (8) -> 42)
type eth_header_type is array(0 to 83) of std_logic_vector(3 downto 0);
constant eth_header: eth_header_type := (
-- Destination Ether: 00:1B:21:19:73:15 (devbak)
-- Destination Ether: 00:04:23:ac:df:87 (mercurius)
x"0",x"0", x"0",x"4", x"2",x"3", x"a",x"c", x"d",x"f", x"8",x"7",
-- Source Ether: 08:00:20:C0:FF:EE
x"0",x"8", x"0",x"0", x"2",x"0", x"C",x"0", x"F",x"F", x"E",x"E",
-- Ether type
x"0",x"8", x"0",x"0",
-- IP header
x"4",x"5", x"0",x"0", x"0",x"8", x"2",x"0", x"0",x"0", x"0",x"0",
x"0",x"0", x"0",x"0", x"4",x"0", x"1",x"1", x"5",x"A", x"C",x"5",
-- Source IP (10.1.2.4), Dest IP (10.1.2.3)
x"0",x"A", x"0",x"1", x"0",x"2", x"0",x"4", x"0",x"A", x"0",x"1", x"0",x"2", x"0",x"3",
-- UDP header
x"2",x"3", x"2",x"3", x"5",x"6", x"5",x"6", x"0",x"8", x"0",x"C", x"0",x"0", x"0",x"0");
constant eth_header_len: integer := 84; -- Number of nibbles
signal crc_calc: std_logic_vector(31 downto 0);
constant tx_tail: integer := 200;
type tx_state_type is (preamble, header, count, data, crc, tail, idle);
signal tx_state: tx_state_type := idle;
signal tx_cnt: unsigned (12 downto 0) := (others => '0');
signal tx_start1: std_logic := '0';
signal tx_start2: std_logic := '0';
signal pkt_cnt: unsigned(31 downto 0) := (others => '0');
begin
tx_payload_ctr <= std_logic_vector(tx_cnt);
process(clk)
variable txd: std_logic_vector(3 downto 0);
begin
if clk'event and clk='1' then
tx_start1 <= tx_start;
tx_start2 <= tx_start1;
case tx_state is
when preamble =>
tx_en <= '1';
tx_d <= eth_preamble(to_integer(tx_cnt(7 downto 1) & not tx_cnt(0)));
if tx_cnt < 15 then
tx_cnt <= tx_cnt + 1;
else
tx_cnt <= (others => '0');
tx_state <= header;
crc_calc <= (others => '1'); -- Preset the CRC with all '1'
end if;
when header =>
tx_en <= '1';
txd := eth_header(to_integer(tx_cnt(7 downto 1) & not tx_cnt(0)));
tx_d <= txd;
crc_calc <= nextCRC32_D4(txd, crc_calc);
if tx_cnt < eth_header_len - 1 then
tx_cnt <= tx_cnt + 1;
else
tx_cnt <= (others => '0');
tx_state <= count;
end if;
when count =>
tx_en <= '1';
tx_cnt <= tx_cnt + 1;
case tx_cnt is
when "0000000000000" =>
txd := std_logic_vector(pkt_cnt(27 downto 24));
when "0000000000001" =>
txd := std_logic_vector(pkt_cnt(31 downto 28));
when "0000000000010" =>
txd := std_logic_vector(pkt_cnt(19 downto 16));
when "0000000000011" =>
txd := std_logic_vector(pkt_cnt(23 downto 20));
when "0000000000100" =>
txd := std_logic_vector(pkt_cnt(11 downto 8));
when "0000000000101" =>
txd := std_logic_vector(pkt_cnt(15 downto 12));
when "0000000000110" =>
txd := std_logic_vector(pkt_cnt (3 downto 0));
when others =>
txd := std_logic_vector(pkt_cnt(7 downto 4));
tx_cnt <= (others => '0');
tx_state <= data;
end case;
crc_calc <= nextCRC32_D4(txd, crc_calc);
tx_d <= txd;
when data =>
tx_en <= '1';
-- txd := eth_data(to_integer(tx_cnt(7 downto 1) & not tx_cnt(0)));
txd := tx_payload;
tx_d <= txd;
crc_calc <= nextCRC32_D4(txd, crc_calc);
if tx_cnt < eth_data_len - 1 then
tx_cnt <= tx_cnt + 1;
else
tx_cnt <= (others => '0');
tx_state <= crc;
end if;
when crc =>
tx_en <= '1';
tx_cnt <= tx_cnt + 1;
case tx_cnt is
when "0000000000000" =>
txd := crc_calc(31 downto 28);
when "0000000000001" =>
txd := crc_calc(27 downto 24);
when "0000000000010" =>
txd := crc_calc(23 downto 20);
when "0000000000011" =>
txd := crc_calc(19 downto 16);
when "0000000000100" =>
txd := crc_calc(15 downto 12);
when "0000000000101" =>
txd := crc_calc(11 downto 8);
when "0000000000110" =>
txd := crc_calc(7 downto 4);
when others =>
txd := crc_calc(3 downto 0);
tx_cnt <= (others => '0');
tx_state <= tail;
end case;
-- Invert the CRC before transmitting
-- Bitswap so bit C(32) is the first to be transmitted
tx_d(0) <= not txd(3);
tx_d(1) <= not txd(2);
tx_d(2) <= not txd(1);
tx_d(3) <= not txd(0);
when tail =>
tx_en <= '0';
tx_d <= "0000";
if tx_cnt < tx_tail - 1 then
tx_cnt <= tx_cnt + 1;
else
tx_cnt <= (others => '0');
pkt_cnt <= pkt_cnt + 1;
tx_state <= idle;
end if;
when idle =>
tx_en <= '0';
tx_d <= "0000";
if tx_start2 = '1' then
tx_state <= preamble;
end if;
end case;
end if;
end process;
end Behavioral;
vhdl work "../common/PCK_CRC32_D4.vhd"
vhdl work "../common/LCD_Controller.vhd"
vhdl worl "LCD_Driver.vhd"
vhdl work "eth_tx.vhd"
vhdl work "main.vhd"
NET "eth*" IOSTANDARD = "LVCMOS18";
NET "eth*" FAST;
NET "eth_rst" LOC = G4;
#NET "eth_rx_clk" LOC = P1;
#NET "eth_rx_clk" TNM_NET = "eth_rx_clk";
#TIMESPEC "TS_eth_rx_clk" = PERIOD "eth_rx_clk" 125 MHz HIGH 50%;
#NET "eth_rx_dv" LOC=D1;
#NET "eth_rx_er" LOC=J3;
#NET "eth_rx_d<0>" LOC = C2;
#NET "eth_rx_d<1>" LOC = G2;
#NET "eth_rx_d<2>" LOC = G5;
#NET "eth_rx_d<3>" LOC = D2;
#NET "eth_rx_d<4>" LOC = AB3;
#NET "eth_rx_d<5>" LOC = AA4;
#NET "eth_rx_d<6>" LOC = AB4;
#NET "eth_rx_d<7>" LOC = Y4;
NET "eth_tx_en" LOC = D3;
NET "eth_tx_clk" LOC = P2;
NET "eth_tx_clk" TNM_NET = "eth_tx_clk";
OFFSET = out 10ns after "eth_tx_clk";
#NET "eth_tx_clk" CLOCK_DEDICATED_ROUTE = FALSE;
TIMESPEC "TS_eth_tx_clk" = PERIOD "eth_tx_clk" 25 MHz HIGH 50%;
NET "eth_tx_d<0>" LOC = J8;
NET "eth_tx_d<1>" LOC = J9;
NET "eth_tx_d<2>" LOC = B2;
NET "eth_tx_d<3>" LOC = B1;
#NET "eth_tx_d<4>" LOC = G6;
#NET "eth_tx_d<5>" LOC = H7;
#NET "eth_tx_d<6>" LOC = K9;
#NET "eth_tx_d<7>" LOC = K8;
#NET "vga_clk" LOC = P26;
#NET "vga_clk" TNM_NET = "vga_clk";
#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 25 MHz HIGH 50%;
#NET "vga_clk" CLOCK_DEDICATED_ROUTE = FALSE;
#NET "vga_blue<0>" LOC = L22;
#NET "vga_blue<1>" LOC = K21;
#NET "vga_blue<2>" LOC = G23;
#NET "vga_blue<3>" LOC = G24;
#NET "vga_green<0>" LOC = M19;
#NET "vga_green<1>" LOC = M18;
#NET "vga_green<2>" LOC = J23;
#NET "vga_green<3>" LOC = J22;
#NET "vga_hsync" LOC = K26;
#NET "vga_red<0>" LOC = L20;
#NET "vga_red<1>" LOC = K20;
#NET "vga_red<2>" LOC = F25;
#NET "vga_red<3>" LOC = F24;
#NET "vga_vsync" LOC = K25;
NET "leds*" IOSTANDARD = "LVCMOS33";
NET "leds<0>" LOC = P18;
NET "leds<1>" LOC = P25;
NET "leds<2>" LOC = N19;
NET "leds<3>" LOC = K22;
NET "leds<4>" LOC = H20;
NET "leds<5>" LOC = G21;
NET "leds<6>" LOC = D24;
NET "leds<7>" LOC = D25;
#INST "Mram_vram*" LOC=RAMB16_X2Y*,RAMB16_X3Y*;
#INST "vga_clk_dcm/DCM_SP_inst" LOC=DCM_X2Y0,DCM_X2Y3,DCM_X1Y0,DCM_X1Y3;
#NET "clk" LOC= F13;
NET "clk" LOC=K14;
NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 140 MHz HIGH 50%;
NET "adc*" IOSTANDARD = "LVCMOS33";
OFFSET = IN 2 ns before clk;
#TIMESPEC TS_adc_clk_sig = PERIOD "adc_clk_sig" 62.5MHz HIGH 50%;
NET "adc_clk" LOC = AA22;
NET "adc_clk" FAST;
NET "adc_a<0>" LOC = U18;
NET "adc_a<1>" LOC = U19;
NET "adc_a<2>" LOC = Y23;
NET "adc_a<3>" LOC = Y22;
NET "adc_a<4>" LOC = T20;
NET "adc_a<5>" LOC = U21;
NET "adc_a<6>" LOC = Y25;
NET "adc_a<7>" LOC = Y24;
NET "adc_a<8>" LOC = T17;
NET "adc_a<9>" LOC = T18;
#NET "adc_b<0>" LOC = AA25;
#NET "adc_b<1>" LOC = AA24;
#NET "adc_b<2>" LOC = AA23;
#NET "adc_b<3>" LOC = V21;
#NET "adc_b<4>" LOC = U20;
#NET "adc_b<5>" LOC = AB24;
#NET "adc_b<6>" LOC = AB23;
#NET "adc_b<7>" LOC = AB26;
#NET "adc_b<8>" LOC = AC26;
#NET "adc_b<9>" LOC = V24;
NET "LCD_clk" LOC = "P26";
NET "LCD_clk" TNM_NET = "LCD_clk";
TIMESPEC "TS_lcd_clk" = PERIOD "LCD_clk" 26 MHz HIGH 50%; # 25.175
NET "LCD_clk" IOSTANDARD = LVCMOS33;
NET "LCD_RS" LOC = "AB15" ; # 4
NET "LCD_RW" LOC = "AF24"; # 5
NET "LCD_E" LOC = "AE24" ; # 6
#NET "Reset" LOC = "M13" ; # Button 0
#NET "LCD_Data<0>" LOC = "A4" ; # 7
#NET "LCD_Data<1>" LOC = "A3" ; # 8
#NET "LCD_Data<2>" LOC = "C9" ; # 9
#NET "LCD_Data<3>" LOC = "C8" ; # 10
NET "LCD_Data<4>" LOC = "W20" ; # 11
NET "LCD_Data<5>" LOC = "W21" ; # 12
NET "LCD_Data<6>" LOC = "AD26" ; # 13
NET "LCD_Data<7>" LOC = "AC25" ; # 14
NET "LCD*" IOSTANDARD = LVCMOS33 | FAST;
-w
-g DebugBitstream:No
-g Binary:no
-g CRC:Enable
-g Reset_on_err:No
-g ConfigRate:6
-g ProgPin:PullUp
-g DonePin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFFFFFF
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6