Commit cf9eaef3 authored by Paul Boven's avatar Paul Boven
Browse files

Brought readme up-to-date

parent 62078b2e
......@@ -10,8 +10,8 @@ Design and realization by Paul Boven (p.boven@xs4all.nl).
This repository will contain the VHDL sources and helper scripts, PCB design files, and photographs.
## Current status: first firmware (2048 bins) succesfully synthesized
Haven't made a bitstream yet, or tested it on the hardware.
## Current status: All 3 firmwares synthesized and built.
Line mode succesfully verified against version compiled on earlier toolchain
### Specifications:
* 70 MS/s, real
......@@ -20,6 +20,11 @@ Haven't made a bitstream yet, or tested it on the hardware.
* 1Gb/s 1000base-T (RJ-45) Ethernet
* External clock (140 MHz)
### Personalities:
* Pulsar mode: 256 spectral bins, 2136 spectra/second
* Line mode: 2048 spectral bins, 267 spectra/second
* Raw mode: unprocessed 70MS/s 10bit, 700Mb/s output
### Main components:
* Xilinx Spartan-3 1800a DSP kit
* Xilinx Spartan-3 1800a DSP FPGA
......@@ -32,14 +37,11 @@ Haven't made a bitstream yet, or tested it on the hardware.
* Make (project is controlled through a Makefile, not ISE)
### TODO:
* Add the other existing firmwares
* Pulsar mode (256 bins)
* Raw mode (70MS/s * 10 bits)
* Convert all firmwares to use 1Gb/s Ethernet
* Update and merge current firmwares, single Makefile, code re-use
* Add WOLA to the FFT-baased backends
* Add WOLA to the FFT-based backends
* New firmwares:
* Digital Down Converter (DDC) for use with GnuRadio and SETI@home
* GPS cross correlation or squaring receiver (for cross-scans)
* Run from 10MHz clock instead of 140 MHz?
* Run from 10MHz clock instead of 140 MHz
* Absolute time or PPS input
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment