Cleaning up the VHDL dependencies and FFT core

VHDL/FFT_stream.xco

+##############################################################
+#
+# Xilinx Core Generator version K.39
+# Date: Tue Dec  2 21:55:35 2008
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = True
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc3sd1800a
+SET devicefamily = spartan3adsp
+SET flowvendor = Foundation_iSE
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = fg676
+SET removerpms = False
+SET simulationfiles = Behavioral
+SET speedgrade = -4
+SET verilogsim = True
+SET vhdlsim = True
+# END Project Options
+# BEGIN Select
+SELECT Fast_Fourier_Transform family Xilinx,_Inc. 6.0
+# END Select
+# BEGIN Parameters
+CSET ce=false
+CSET channels=1
+CSET component_name=FFT_stream
+CSET cyclic_prefix_insertion=false
+CSET data_format=fixed_point
+CSET fast_butterfly=false
+CSET fast_complex_mult=false
+CSET implementation_options=pipelined_streaming_io
+CSET input_width=16
+CSET memory_options_data=block_ram
+CSET memory_options_hybrid=true
+CSET memory_options_phase_factors=block_ram
+CSET memory_options_reorder=block_ram
+CSET number_of_stages_using_block_ram_for_data_and_phase_factors=5
+CSET optimize_for_speed_using_xtreme_dsp_slices=false
+CSET output_ordering=natural_order
+CSET ovflo=false
+CSET phase_factor_width=16
+CSET rounding_modes=truncation
+CSET run_time_configurable_transform_length=false
+CSET scaling_options=unscaled
+CSET sclr=false
+CSET target_clock_frequency=125
+CSET target_data_throughput=50
+CSET transform_length=4096
+# END Parameters
+GENERATE
+# CRC: dc5a4490
+

VHDL/Makefile

@@ -8,7 +8,7 @@ all: main.twr main.bit
 xst/projnav.tmp:
 	mkdir -p xst/projnav.tmp
 # XST
-main.ngc:	main.xst main.prj main.vhd FFT_stream.vhd eth_tx.vhd PCK_CRC32_D4.vhd LCD_Driver.vhd LCD_Controller.vhd window.vhd main.lso xst/projnav.tmp
+main.ngc:	main.xst main.prj main.vhd FFT_stream.xco eth_tx.vhd PCK_CRC32_D4.vhd LCD_Driver.vhd LCD_Controller.vhd window.vhd main.lso xst/projnav.tmp
 	xst -ifn main.xst -ofn main.syr
 
 # TODO: generate the window file automatically

VHDL/main.prj

@@ -2,6 +2,5 @@ vhdl work "PCK_CRC32_D4.vhd"
 vhdl work "LCD_Controller.vhd"
 vhdl work "LCD_Driver.vhd"
 vhdl work "window.vhd"
-vhdl work "FFT_stream.vhd"
 vhdl work "eth_tx.vhd"
 vhdl work "main.vhd"