Commit e52094fc authored by Paul Boven's avatar Paul Boven
Browse files

Changed to two-stage decimation with 0.01dB flatness, 60dB out-of-band suppression

parent 592db41c
......@@ -5,7 +5,7 @@
# http://www.camras.nl/
# http://gitlab.camras.nl/paulb/DT-Backend-S3A1800dsp
SUBDIRS = S3ADC_v03 S3ADC-4k S3ADC_1G
SUBDIRS = S3ADC_v03 S3ADC-4k S3ADC_1G S3ADC_SDR_5
SUBCLEAN = $(addsuffix .clean,$(SUBDIRS))
.PHONY: all clean $(SUBDIRS) $(SUBCLEAN)
......
......@@ -3,22 +3,25 @@
# and sends it out over the 1Gb/s ethernet
# $Id: Makefile,v 1.1 2012/01/03 21:00:36 paul Exp paul $
all: main.twr main.bit
all: main.twr main.bit SDR-5M.bit
clean:
rm -rf raw.bit main.bit main.twr main.bgn main.bld main.cgc main.cgp main.drc main.ncd main.ngc main.ngd main.ngr main.pad main.par main.pcf man.twx main.syr main.twr main.twx main.unroutes main.xpi .lso main.ptwx main_bitgen.xwbt main_map.map main_map.mrp main_map.ncd main_map.ngm main_map.xrpt main_ngdbuild.xrpt main_pad.csv main_pad.txt main_par.xrpt main_summary.xml main_usage.xml main_xst.xrpt tmp/ _nog/ _xmsgs/ usage_statistics_webtalk.html webtalk.log xlnx_auto_0_xdb coregen.log fir_compiler_v5_0.asy fir_compiler_v5_0COEFF_auto0_0.mif fir_compiler_v5_0filt_decode_rom.mif fir_compiler_v5_0_flist.txt fir_compiler_v5_0.gise fir_compiler_v5_0.mif fir_compiler_v5_0.ngc fir_compiler_v5_0_readme.txt fir_compiler_v5_0.vhd fir_compiler_v5_0.vho fir_compiler_v5_0.xise fir_compiler_v5_0_xmdf.tcl xst/ fir_compiler_v5_0COEFF*
rm -rf raw.bit main.bit main.twr main.bgn main.bld main.cgc main.cgp main.drc main.ncd main.ngc main.ngd main.ngr main.pad main.par main.pcf man.twx main.syr main.twr main.twx main.unroutes main.xpi .lso main.ptwx main_bitgen.xwbt main_map.map main_map.mrp main_map.ncd main_map.ngm main_map.xrpt main_ngdbuild.xrpt main_pad.csv main_pad.txt main_par.xrpt main_summary.xml main_usage.xml main_xst.xrpt tmp/ _nog/ _xmsgs/ usage_statistics_webtalk.html webtalk.log xlnx_auto_0_xdb coregen.log fir_A.asy fir_B.asy fir_Afilt_decode_rom.mif fir_Bfilt_decode_rom.mif fir_A_flist.txt fir_B_flist.txt fir_A.gise fir_B.gise fir_A.mif fir_B.mif fir_A.ngc fir_B.ngc fir_A_readme.txt fir_B_readme.txt fir_A.vhd fir_B.vhd fir_A.vho fir_B.vho fir_A.xise fir_B.xise fir_A_xmdf.tcl fir_B_xmdf.tcl xst/ fir_ACOEFF* fir_BCOEFF* SDR-5M.bit
xst/projnav.tmp:
mkdir -p xst/projnav.tmp
fir_compiler_v5_0.ngc: fir_compiler_v5_0.xco
coregen -b fir_compiler_v5_0.xco -p main.prj
fir_A.ngc: fir_A.xco fir_A.coe
coregen -b fir_A.xco -p main.prj
fir_B.ngc: fir_B.xco fir_B.coe
coregen -b fir_B.xco -p main.prj
lo.vhdl: lo.vhdl.templ lo.pl
./lo.pl lo.vhdl.templ > lo.vhdl
# XST
main.ngc: main.xst main.prj main.vhd LCD_Driver.vhd LCD_Controller.vhd fir_compiler_v5_0.ngc xst/projnav.tmp
main.ngc: main.xst main.prj main.vhd LCD_Driver.vhd LCD_Controller.vhd fir_A.ngc fir_B.ngc xst/projnav.tmp
xst -ifn main.xst -ofn main.syr
# Ngdbuild
......
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##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Thu Dec 15 21:27:47 2016
# Date: Sun Dec 18 09:36:56 2016
#
##############################################################
#
......@@ -44,8 +44,8 @@ CSET bestprecision=false
CSET chan_in_adv=0
CSET clock_frequency=140
CSET coefficient_buffer_type=Automatic
CSET coefficient_file=./fir_filter.coe
CSET coefficient_fractional_bits=18
CSET coefficient_file=./fir_A.coe
CSET coefficient_fractional_bits=0
CSET coefficient_reload=false
CSET coefficient_sets=1
CSET coefficient_sign=Signed
......@@ -53,13 +53,13 @@ CSET coefficient_structure=Inferred
CSET coefficient_width=16
CSET coefficientsource=COE_File
CSET coefficientvector=6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6
CSET columnconfig=8
CSET component_name=fir_compiler_v5_0
CSET columnconfig=5
CSET component_name=fir_A
CSET data_buffer_type=Automatic
CSET data_fractional_bits=0
CSET data_sign=Signed
CSET data_width=16
CSET decimation_rate=14
CSET decimation_rate=7
CSET displayreloadorder=false
CSET filter_architecture=Systolic_Multiply_Accumulate
CSET filter_selection=1
......@@ -80,7 +80,7 @@ CSET optimization_goal=Speed
CSET output_buffer_type=Automatic
CSET output_rounding_mode=Truncate_LSBs
CSET output_width=16
CSET passband_max=0.4
CSET passband_max=0.5
CSET passband_min=0.0
CSET preference_for_other_storage=Automatic
CSET quantization=Maximize_Dynamic_Range
......@@ -91,7 +91,7 @@ CSET sample_frequency=70
CSET sampleperiod=1
CSET sclr_deterministic=false
CSET stopband_max=1.0
CSET stopband_min=0.6
CSET stopband_min=0.5
CSET usechan_in_adv=false
CSET zero_pack_factor=1
# END Parameters
......@@ -99,4 +99,4 @@ CSET zero_pack_factor=1
MISC pkg_timestamp=2013-10-13T18:46:09Z
# END Extra information
GENERATE
# CRC: 8fb41bbc
# CRC: 150ee687
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##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Sun Dec 18 09:38:04 2016
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fir_compiler:5.0
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc3sd1800a
SET devicefamily = spartan3adsp
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fg676
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -5
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT FIR_Compiler family Xilinx,_Inc. 5.0
# END Select
# BEGIN Parameters
CSET allow_rounding_approximation=false
CSET bestprecision=false
CSET chan_in_adv=0
CSET clock_frequency=140
CSET coefficient_buffer_type=Automatic
CSET coefficient_file=./fir_B.coe
CSET coefficient_fractional_bits=0
CSET coefficient_reload=false
CSET coefficient_sets=1
CSET coefficient_sign=Signed
CSET coefficient_structure=Inferred
CSET coefficient_width=16
CSET coefficientsource=COE_File
CSET coefficientvector=6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6
CSET columnconfig=8
CSET component_name=fir_B
CSET data_buffer_type=Automatic
CSET data_fractional_bits=0
CSET data_sign=Signed
CSET data_width=16
CSET decimation_rate=2
CSET displayreloadorder=false
CSET filter_architecture=Systolic_Multiply_Accumulate
CSET filter_selection=1
CSET filter_type=Decimation
CSET gui_behaviour=Coregen
CSET hardwareoversamplingrate=1
CSET has_ce=false
CSET has_data_valid=false
CSET has_nd=true
CSET has_sclr=false
CSET input_buffer_type=Automatic
CSET inter_column_pipe_length=4
CSET interpolation_rate=1
CSET multi_column_support=Disabled
CSET number_channels=1
CSET number_paths=1
CSET optimization_goal=Speed
CSET output_buffer_type=Automatic
CSET output_rounding_mode=Truncate_LSBs
CSET output_width=16
CSET passband_max=0.5
CSET passband_min=0.0
CSET preference_for_other_storage=Automatic
CSET quantization=Maximize_Dynamic_Range
CSET rate_change_type=Integer
CSET ratespecification=Frequency_Specification
CSET registered_output=true
CSET sample_frequency=10
CSET sampleperiod=1
CSET sclr_deterministic=false
CSET stopband_max=1.0
CSET stopband_min=0.5
CSET usechan_in_adv=false
CSET zero_pack_factor=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2013-10-13T18:46:09Z
# END Extra information
GENERATE
# CRC: 8a341368